Complex digital systems are normally made up of a certain number of devices (cores, peripheral memories, etc.), which exchange information. Frequently, such devices operate at different clock frequencies, with frequencies that may be defined as semi-synchronous, in the sense that they refer to clocks of different value but with certain given phase relations between them. For example, the interconnection system developed by the present Assignee under the commercial name STBus Interconnect can be used in conjunction with the CPU known as ST40, also produced by the present Assignee.
Such a CPU needs to be able to operate on the basis of different frequency ratios, namely in conditions in which the clock of the interconnection system has a ratio of 2/3, one half, or equal to the clock of the CPU. Under such conditions, there exists the need to have available a synchronization mechanism that is able to adequately synchronize the two clock domains (i.e. that of the CPU and that of the interconnection bus), at the same time reducing occupation of space on the chip and preventing latency phenomena from arising.
No currently known approach is able to provide a satisfactory synchronization. For example, the approach known as “asynchronous bridge” corresponds to a frequency converter of altogether general application. This approach, however, involves intrinsic drawbacks, linked, for instance, to the control circuitry (which is somewhat complex), to the occupation of space (which is, in turn, linked both to the complexity of the control logic and to the use of memory elements), as well as to latency phenomena (due to the use of stages that carry out a re-timing function).
Another known approach is the one known as “dual-port memory”. This is simply a memory that implements a queue of a first-in first-out (FIFO) type, with the use of two distinct pointers, one for loading the data and the other for reading the data. However, also this approach presents intrinsic drawbacks linked to the use of memory elements and latency.
There are then known devices that are generically referred to as synchronizers, which include networks of specific flip-flops appropriately connected together. This approach entails a smaller occupation of area on the chip, but is not exempt from the drawback of latency associated to the presence of re-timing stages.